Design a half adder circuit using Verilog. A half adder is a combinational circuit that computes the sum of two single-bit binary numbers. It has two inputs (A and B) and two outputs:

SUM: the least significant bit of the addition

CARRY: the carry-out of the addition

Your task is to implement the logic using only basic gates (AND, OR, XOR, NOT).

✅ Input:
a: 1-bit input

b: 1-bit input

✅ Output:
sum: 1-bit output (a ⊕ b)

carry: 1-bit output (a · b)