Design a positive-edge-triggered D flip-flop with a synchronous active-high reset: on each rising clock edge q takes the value of d, unless rst is 1, in which case q becomes 0.

Inputs: clk, rst, d.
Output: q.

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 40 cycles.