Design a D flip-flop with a clock enable and an asynchronous active-high reset. When arst is 1, q goes to 0 immediately, without waiting for a clock edge. Otherwise, on a rising clock edge, q takes d only if en is 1; with en at 0 it holds its value.

Inputs: clk, arst, en, d.
Output: q.

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 48 cycles.