Design a JK flip-flop with a synchronous active-high reset. On each rising clock edge: J=0,K=0 holds; J=0,K=1 clears q to 0; J=1,K=0 sets q to 1; J=1,K=1 toggles q.

Inputs: clk, rst, j, k.
Output: q.

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 48 cycles.