Design a 4-bit register. On a rising clock edge it stores d when load is 1 and keeps its value when load is 0. A synchronous active-high reset clears it to 0000.

Inputs: clk, rst, load, d (4 bits).
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 48 cycles.