Design a 4-bit shift register. On each rising clock edge with en at 1, the contents shift left by one and the serial input enters at bit 0: q becomes {q[2:0], sin}. With en at 0 it holds. A synchronous reset clears it.

Inputs: clk, rst, en, sin.
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 48 cycles.