Design a 4-bit universal shift register controlled by a 2-bit mode: 00 hold, 01 shift right (sin enters at bit 3), 10 shift left (sin enters at bit 0), 11 parallel load from d. A synchronous reset clears it.

Inputs: clk, rst, mode (2 bits), sin, d (4 bits).
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 64 cycles.