Design a 4-bit binary up counter with an enable. On each rising clock edge with en at 1 the count increases by one, wrapping from 1111 to 0000. With en at 0 it holds. A synchronous reset clears it.

Inputs: clk, rst, en.
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 64 cycles.