Design a 4-bit counter that counts up when up is 1 and down when up is 0, on rising clock edges where en is 1. It wraps in both directions (1111 + 1 = 0000, 0000 - 1 = 1111). A synchronous reset clears it.

Inputs: clk, rst, en, up.
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 80 cycles.