Design a decade counter: it counts 0 to 9 and then returns to 0. It advances on rising clock edges where en is 1. The output tc (terminal count) is 1 whenever the count is 9. A synchronous reset clears the count.

Inputs: clk, rst, en.
Outputs: q (4 bits), tc.

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 56 cycles.