Design a 4-bit ring counter: a single 1 circulates through the four bits. Reset loads 0001; on every following rising clock edge the pattern rotates left: 0001, 0010, 0100, 1000, 0001, and so on.

Inputs: clk, rst.
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 24 cycles.