Design a 4-bit Johnson (twisted ring) counter. Reset clears it to 0000; on each rising clock edge it shifts left and feeds the inverse of the top bit into bit 0, giving the eight-state sequence 0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000.

Inputs: clk, rst.
Output: q (4 bits).

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 28 cycles.