Design a Moore finite state machine that watches a serial input and detects the bit sequence 1011, with overlap allowed (in 1011011 the sequence occurs twice, sharing a 1). The output z is 1 for one clock cycle after the fourth bit of a match has been sampled; in other words z is 1 exactly when the last four sampled bits were 1,0,1,1. A synchronous reset returns the machine to its start state and forgets the history.

Inputs: clk, rst, din.
Output: z.

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 72 cycles.