Design a circuit that produces a one-cycle pulse when its input goes from 0 to 1. Register the input each clock; the registered output pulse is 1 on the cycle after a rising edge was sampled (the sampled value is 1 and the previously sampled value was 0), and 0 otherwise. A synchronous reset clears both registers.

Inputs: clk, rst, sig.
Output: pulse.

The testbench drives the inputs on the falling clock edge and checks the outputs just before and just after every rising edge, against a reference model, for 56 cycles.