About Indicore

Indicore is a place to learn digital design and Verilog by doing it: you write hardware, run it in your browser, and see what it does. There is nothing to install.

This page is the reference for what the site offers. Everything under Available today works now. Everything under Planned does not exist yet; it is listed so you know where the site is heading, with no dates promised.

Available today

Practice problems, graded

67 Verilog problems: 52 on combinational logic and 15 on sequential logic, from a half adder to state machines and a small memory. Your design is simulated against a testbench and compared with a reference solution, so you know at once whether it is right.

Browse the problems

Online Verilog simulator

A playground with a code editor, multi-file projects, compiler output and a waveform viewer. Write your own design and testbench and run them. No account is needed.

Open the playground

Waveform viewer

Every run shows its signals over time: zoom and pan, buses in hex, decimal or binary, a cursor with values, and two markers to measure between.

Courses

Lessons where the circuits and simulations are part of the page: toggle the inputs of a gate, wire a circuit yourself, edit Verilog and run it, all inside the chapter. The first course, on digital design from gates to state machines, is being written and will be free.

See the courses

Progress and leaderboard

With a free account the site remembers which problems you have solved and where you are in each course, and you appear on the leaderboard.

See the leaderboard

Contributed content

Problems and courses can be written by contributors, alone or with co-authors. Nothing reaches the public until a moderator has reviewed and published it, and nobody approves their own work.

What the simulator supports

Designs run on Icarus Verilog 11. That means:

  • Supported: Verilog-2005, and the commonly used parts of SystemVerilog for design (logic, always_ff, always_comb, packed arrays, parameters).
  • Not supported today: UVM, SystemVerilog classes and constrained-random verification, assertions (SVA), VHDL, and vendor libraries.
  • Limits: each run is short and small by design (a few seconds, modest memory). The simulator is for learning and for checking ideas, not for large designs.

Every run happens in an isolated sandbox with no network or file access, so it is safe to experiment.

Planned

None of the following is available yet.

  • More courses. After the free digital design course: verification and testbenches, state machines and datapaths, memories and FIFOs, and project courses such as image processing, FFT and JPEG.
  • Subscriptions. Practice problems, the playground and the first course stay free. Later courses are planned as paid, with free preview chapters. See the plans page; subscriptions are not open yet.
  • UVM and fuller SystemVerilog. A second simulator to run verification code that Icarus Verilog cannot.
  • More problems, including sequential design, memories and interview-style questions.
  • Saved work. Keeping your playground projects and results between visits.
  • FPGA flow. Synthesising a design and seeing what it becomes.
  • An AI design assistant to explain errors and review your code.

Principles

  • No advertising. The site is free of ads and intends to stay that way.
  • Say only what is true. If a feature is not listed under “Available today”, the site does not have it.
  • Learn by running. Every idea in a lesson should be something you can try on the same page.