Sequential Logic

Registers & Shift Registers

  • D Flip-Flop
    Design a positive-edge-triggered D flip-flop with a synchronous active-high reset: on each rising clock edge q takes the value of …
    by Indicore
    Solve
  • D Flip-Flop with Enable and Asynchronous Reset
    Design a D flip-flop with a clock enable and an asynchronous active-high reset. When arst is 1, q goes to …
    by Indicore
    Solve
  • T Flip-Flop
    Design a toggle flip-flop with a synchronous active-high reset: on each rising clock edge q inverts when t is 1 …
    by Indicore
    Solve
  • JK Flip-Flop
    Design a JK flip-flop with a synchronous active-high reset. On each rising clock edge: J=0,K=0 holds; J=0,K=1 clears q to …
    by Indicore
    Solve
  • 4-bit Register with Load
    Design a 4-bit register. On a rising clock edge it stores d when load is 1 and keeps its value …
    by Indicore
    Solve
  • 4-bit Shift Register (serial in, parallel out)
    Design a 4-bit shift register. On each rising clock edge with en at 1, the contents shift left by one …
    by Indicore
    Solve
  • Universal Shift Register
    Design a 4-bit universal shift register controlled by a 2-bit mode: 00 hold, 01 shift right (sin enters at bit …
    by Indicore
    Solve

Counters

  • 4-bit Up Counter
    Design a 4-bit binary up counter with an enable. On each rising clock edge with en at 1 the count …
    by Indicore
    Solve
  • 4-bit Up/Down Counter
    Design a 4-bit counter that counts up when up is 1 and down when up is 0, on rising clock …
    by Indicore
    Solve
  • Mod-10 (Decade) Counter
    Design a decade counter: it counts 0 to 9 and then returns to 0. It advances on rising clock edges …
    by Indicore
    Solve
  • 4-bit Ring Counter
    Design a 4-bit ring counter: a single 1 circulates through the four bits. Reset loads 0001; on every following rising …
    by Indicore
    Solve
  • 4-bit Johnson Counter
    Design a 4-bit Johnson (twisted ring) counter. Reset clears it to 0000; on each rising clock edge it shifts left …
    by Indicore
    Solve

Finite State Machines

  • Sequence Detector (1011)
    Design a Moore finite state machine that watches a serial input and detects the bit sequence 1011, with overlap allowed …
    by Indicore
    Solve
  • Rising Edge Detector
    Design a circuit that produces a one-cycle pulse when its input goes from 0 to 1. Register the input each …
    by Indicore
    Solve

Memory Modules

  • 16x4 Synchronous RAM
    Design a synchronous single-port RAM with 16 words of 4 bits. On each rising clock edge: if we is 1, …
    by Indicore
    Solve